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VSC8601XKN 参数 Datasheet PDF下载

VSC8601XKN图片预览
型号: VSC8601XKN
PDF下载: 下载PDF文件 查看货源
内容描述: VSC8601 10/100 / 1000BASE -T PHY与MAC RGMII接口 [VSC8601 10/100/1000BASE-T PHY with RGMII MAC Interface]
分类和应用: 网络接口电信集成电路电信电路局域网(LAN)标准以太网:16GBASE-T
文件页数/大小: 102 页 / 861 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
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VSC8601 Datasheet  
Functional Descriptions  
MDC to the next rising edge of MDC. When data is being written to the PHY, it must be  
valid around the rising edge of MDC.  
Idle The sequence is repeated.  
3.11.2  
SMI Interrupts  
The SMI also includes an output interrupt signal, MDINT, for signaling the station  
manager when certain events occur in the PHY.  
The MDINT pin can be configured for open-drain (active-low) by tying the pin to a  
pull-up resistor and to VDDIO. The following illustration shows this configuration.  
Figure 10.  
MDINT Configured as an Open-Drain (Active-Low) Pin  
VDDIO  
External Pull-up  
at Station Manager  
for Open-Drain  
(Active Low Mode)  
Interrupt Pin Enable  
(MII Register 25.15)  
MDINT  
MDINT  
(to Station Manager)  
Interrupt Pin Status  
(MII Register 26.15)  
Alternatively, each MDINT pin can be configured for open-source (active-high) by tying  
the pin to a pull-down resistor and to VSS. The following illustration shows this  
configuration.  
Figure 11.  
MDINT Configured as an Open-Source (Active-High) Pin  
VDDIO  
Interrupt Pin Enable  
(MII Register 25.15)  
MDINT  
(to Station Manager)  
MDINT  
Interrupt Pin Status  
External Pull-Down at  
Station Manager  
(MII Register 26.15)  
for Open Source  
(Active-High Mode)  
When a PHY generates an interrupt, the MDINT pin is asserted (driven high or low,  
depending on resistor connection) if the interrupt pin enable bit (MII Register 25.15) is  
set.  
Revision 4.1  
September 2009  
Page 27  
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