VSC8601 Datasheet
Functional Descriptions
3.10.2
Link Partner Wake-Up State
In this state, the PHY attempts to wake up the link partner. FLP bursts are sent on
alternating pairs A and B of the Cat5 media for a duration of two seconds.
In this state, the following functionality is provided:
•
•
SMI interface (MDC, MDIO, MDINT)
CLKOUT
After sending signal energy on the relevant media, the PHY returns to the low-power
state.
3.10.3
Normal Operating State
In this state, the PHY establishes a link with a link partner. When the media is
unplugged or the link partner is powered down, the PHY waits for the duration of the
programmable link status time-out timer, which is set using register bit 28.7 and
bit 28.2. It then enters the low-power state.
3.11
Serial Management Interface
The VSC8601 device includes an IEEE 802.3-compliant serial management interface
(SMI) that is affected by use of its MDC and MDIO pins. The SMI provides access to
device control and status registers. The register set that controls the SMI consists of 32
16-bit registers, including all required IEEE-specified registers. Also, there are
additional pages of registers accessible by means of device register 31.
For more information, see “Extended Page Registers,” page 55.
The SMI is a synchronous serial interface with bidirectional data on the MDIO pin that is
clocked on the rising edge of the MDC pin. The interface can be clocked at a rate from
0 MHz to 25 MHz, depending upon the total load on MDIO. An external, 2 kΩ pull-up
resistor is required on the MDIO pin.
3.11.1
SMI Frames
Data is transferred over the SMI using 32-bit frames with an optional and arbitrary
length preamble. The following illustrations show the SMI frame format for the read
operation and write operation.
Revision 4.1
September 2009
Page 25
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
