VSC8601 Datasheet
Functional Descriptions
the EPG is enabled. If it is necessary to disable the MAC receive pins as well, set
register bit 0.10 to 1.
When the device register bit 29E.14 is set to 1, the PHY begins transmitting Ethernet
packets based on the settings in registers 29E and 30E. These registers set:
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Source and destination addresses for each packet
Packet size
Inter-packet gap
FCS state
Transmit duration
Payload pattern
If register bit 29E.13 is set to 0, register bit 29E.14 is cleared automatically after
30,000,000 packets are transmitted.
3.13.2
CRC Counters
Two separate cyclical redundancy checking (CRC) counters are available in the
VSC8601 device. There is a 14-bit CRC good counter available in register bits 18E.13:0
and a separate 8-bit CRC error counter available in register bits 23E.7:0.
The device CRC counters operate in 10/100/1000BASE-T testing as follows:
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After receiving a packet on the media interface, register bit 18E.15 is set and
cleared after being read. The packet then is counted by either the CRC good
counter or the CRC error counter. Both CRC counters are also automatically cleared
when read.
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The CRC good counter’s highest value is 9,999 packets. Upon receiving the next
packet, the counter clears and continues to count additional packets beyond that
value. The CRC error counter saturates when it reaches its maximum counter limit
of 255 packets.
3.13.3
Far-end Loopback
The far-end loopback testing feature is enabled by setting register bit 27E.10 to 1.
When enabled, it forces incoming data from a link partner on the current media
interface to be retransmitted back to the link partner on the media interface as shown
in the following illustration. In addition, the incoming data also appears on the receive
data pins of the MAC interface. Data present on the transmit data pins of the MAC
interface is ignored when using this testing feature.
Revision 4.1
September 2009
Page 31
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
