VSC838-01
Datasheet
INCHAN0_SDIN
Y5 Y4 Y3 Y2
tsSDIN thSDIN
LOW
Y1 Y0 A5
A4 A3 A2
LOW
A1 A0
tperSCLK
INCHAN1_SCLK
SDOUT
tdsDOUT
Y5 Y4 Y3 Y2
tsLOAD
thLOAD
LOAD
thCS
tsCS
CS
CONFIG
SERIAL
tpwCFG
tsSERIAL
Y(n) = Output Address Bit (n), A(n) = Input Address Bit (n)
Figure 3. Serial Mode (leave ALE_SCN pin LOW during programming)
thSCAN
ALE_SCN
tperSCLK
tsSCAN
INCHAN1_SCLK
SDOUT
tdsDOUT
36
36
36
B3
36
B2
36
LOW
36
B1
36
B0
35
B5
35
B4
35
B3
35
B2
35
LOW
35
B1
35
B0
34
B5
B5
B4
tsSERIAL
SERIAL
MSB of program memory for Activity Monitor Channel
Read-back shift register (483 bits long) is loaded here
on rising edge of INCHAN1_SCLK with SERIAL HIGH
and ALE_SCN LOW.
NOTE: The word pattern during serial read-back will be four valid words followed by four "Don't Care" words.
Figure 4. Serial Readback
7 of 19
VMDS-10195 Revision 4.0
August 19, 2005
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
