VSC838-01
Datasheet
Electrical Specifications
AC Characteristics
All characteristics are specified over the recommended operating conditions.
Table 1. Data Path
Symbol
fRATE
tSKW
tPDAY
tR, tF
tJR
Parameter
Min
Typ
Max
Unit
Gbps
ps
Maximum data rate
3.2
Channel-to-channel delay skew
Propagation delay from an A input to a Y output
High-speed input and output rise/fall times, 20% to 80%1
Output added delay jitter, rms2
300
750
ps
150
10
ps
ps
tJP
Output added delay jitter, peak-to-peak2
40
ps
1. The high-speed input rise/fall time must be ≤150ps.
2. Broadband (unfiltered) deterministic jitter added to a jitter-free input. 2 -1 PRBS data pattern.
23
Table 2. Program Interface Timing
Symbol
tsWR
Parameter
Min
3.35
1.45
6.75
0
Typ
Max
Unit
ns
Setup time from INCHAN[5:0] or OUTCHAN[5:0] to rising edge of WR
Hold time from rising edge of WR to INCHAN[5:0] or OUTCHAN[5:0]
Pulse width (HIGH or LOW) on LOAD
thWR
ns
tpwLW
tsCS
ns
Setup time from CS to falling edge of LOAD or ALE_SCN in parallel, or
rising edge of LOAD in serial mode.
ns
thCS
Hold time of CS rising edge after LOAD or ALE_SCN rising in parallel,
falling edge of LOAD in serial mode, or falling edge of CONFIG in any
mode.
0
ns
tpwCFG
tsSDIN
Pulse width (HIGH or LOW) on CONFIG
6.75
1.65
1.0
ns
ns
ns
ns
ns
ns
ns
Setup time from INCHAN0_SDIN to INCHAN1_SCLK rising
Hold time of INCHAN0_SDIN after INCHAN1_SCLK rising
Minimum period of SCLK in serial mode
thSDIN
tperSCLK
tsLOAD
thLOAD
tsSERIAL
15
Setup time from LOAD to INCHAN1_SCLK rising
Hold time of LOAD after INCHAN1_SCLK rising
1.85
0.95
0.90
Setup time from SERIAL rising to INCHAN1_SCLK rising when entering
serial mode or SERIAL falling to LOAD falling when entering parallel
mode.
thSERIAL
Hold time from INCHAN1_SCLK rising to SERIAL falling when exiting
serial mode.
0
ns
tdsDOUT
tpwINIT
tsSCAN
Delay from INCHAN1_SCLK rising to SDOUT, 20pF load.
Pulse width (HIGH or LOW) on INIT
6.20
ns
ns
ns
6.75
1.65
Setup time from ALE_SCN to INCHAN1_SCLK rising when starting or
completing a serial read-back sequence.
thSCAN
Hold time of ALE_SCN after INCHAN1_SCLK rising when starting or
completing a serial read-back sequence.
1.0
ns
5 of 19
VMDS-10195 Revision 4.0
August 19, 2005
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
