VSC838-01
Datasheet
Table 11. Pin Identifications (continued)
Signal
INCHAN0_SDIN
INCHAN1_SCLK
INCHAN2
INCHAN3
INCHAN4
INCHAN5
INIT
Ball Site
AG24
AF24
AH24
AJ24
I/O
Level
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Analog
Description
Input Channel, Bit 0 and Serial Data in Serial Mode
Input Channel, Bit 1 and Serial Clock in Serial Mode
Input Channel, Bit 2
Input Channel, Bit 3
AD27
AD26
AJ6
Input Channel, Bit 4
Input Channel, Bit 5
INIT=0 Forces “Straight-Through” Program
Input Termination Control. GND = floating input termination,
ITC
AD29
VCC = CML mode. For more information, see Table 7, page 9.
NOTE: Do not connect to VCC or VEE supplies using a high value
resistor. If a resistor is used to connect ITC to VCC or VEE, the resis-
tor value must be < 100Ω..
LOAD
AD28
LVTTL
Rising Edge Writes Data in Parallel Mode. For information about
Serial mode, see Figure 4, page 7.
OUTCHAN0
OUTCHAN1
ACTCHAN
OUTCHAN2
OUTCHAN3
OUTCHAN4
OUTCHAN5
SDOUT
F1
F2
O
O
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Output Channel, Bit 0
Output Channel, Bit 1
F5
Activity Channel Enable Bit, HIGH = Enable
Output Channel, Bit 2
F4
O
O
O
O
F3
Output Channel, Bit 3
A6
Output Channel, Bit 4
B6
Output Channel, Bit 5
AG6
AE6
AD5
Serial Data Out for Serial Mode and Scan
SERIAL = 1 Sets Serial Mode
SERIAL
TERM_CTRL
Output Back-Termination Control. LOW = no back-termination;
HIGH = 50Ω back-termination to VCC. For more information, see
Table 8, page 9.
Table 12. Power Supplies
Signal
Ball Site
Description
NC
D22, AH22, B22, AF22
D20, AH20, B20, AF20
D18, AH18, B18, AF18
D16, AH16, B16, AF16
D14, AH14, B14, AF14
D12, AH12, B12, AF12
D10, AH10, B10, AF10
D8, AH8, B8, AF8
No Connect
E22, AJ22, A22, AE22
E20, AJ20, A20, AE20
E18, AJ18, A18, AE18
E16, AJ16, A16, AE16
E14, AJ14, A14, AE14
E12, AJ12, A12, AE12
E10, AJ10, A10, AE10
E8, AJ8, A8, AE8
14 of 19
VMDS-10195 Revision 4.0
August 19, 2005
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
