VSC838-01
Datasheet
Table 11. Pin Identifications (continued)
Signal
Y3, YN3
Ball Site
G2, G1
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Level
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
Description
High-Speed Data Output Channel 3; True, Complement
High-Speed Data Output Channel 4; True, Complement
High-Speed Data Output Channel 5; True, Complement
High-Speed Data Output Channel 6; True, Complement
High-Speed Data Output Channel 7; True, Complement
High-Speed Data Output Channel 8; True, Complement
High-Speed Data Output Channel 9; True, Complement
High-Speed Data Output Channel 10; True, Complement
High-Speed Data Output Channel 11; True, Complement
High-Speed Data Output Channel 12; True, Complement
High-Speed Data Output Channel 13; True, Complement
High-Speed Data Output Channel 14; True, Complement
High-Speed Data Output Channel 15; True, Complement
High-Speed Data Output Channel 16; True, Complement
High-Speed Data Output Channel 17; True, Complement
High-Speed Data Output Channel 18; True, Complement
High-Speed Data Output Channel 19; True, Complement
High-Speed Data Output Channel 20; True, Complement
High-Speed Data Output Channel 21; True, Complement
High-Speed Data Output Channel 22; True, Complement
High-Speed Data Output Channel 23; True, Complement
High-Speed Data Output Channel 24; True, Complement
High-Speed Data Output Channel 25; True, Complement
High-Speed Data Output Channel 26; True, Complement
High-Speed Data Output Channel 27; True, Complement
High-Speed Data Output Channel 28; True, Complement
High-Speed Data Output Channel 29; True, Complement
High-Speed Data Output Channel 30; True, Complement
High-Speed Data Output Channel 31; True, Complement
High-Speed Data Output Channel 32; True, Complement
High-Speed Data Output Channel 33; True, Complement
High-Speed Data Output Channel 34; True, Complement
High-Speed Data Output Channel 35; True, Complement
Y4, YN4
J28, J29
J4, J5
Y5, YN5
Y6, YN6
J26, J25
J2, J1
Y7, YN7
Y8, YN8
L28, L29
L4, L5
Y9, YN9
Y10, YN10
Y11, YN11
Y12, YN12
Y13, YN13
Y14, YN14
Y15, YN15
Y16, YN16
Y17, YN17
Y18, YN18
Y19, YN19
Y20, YN20
Y21, YN21
Y22, YN22
Y23, YN23
Y24, YN24
Y25, YN25
Y26, YN26
Y27, YN27
Y28, YN28
Y29, YN29
Y30, YN30
Y31, YN31
Y32, YN32
Y33, YN33
Y34, YN34
Y35, YN35
L26, L25
L2, L1
N28, N29
N4, N5
N26, N25
N2, N1
R28, R29
R4, R5
R26, R25
R2, R1
U28, U29
U4, U5
U26, U25
U2, U1
W28, W29
W4, W5
W26, W25
W2, W1
AA28, AA29
AA4 , AA5
AA26, AA25
AA2, AA1
AC28, AC29
AC4, AC5
AC26, AC25
AC2, AC1
Control Pins
ACTCLK
AD2
AD1
LVTTL
LVTTL
LVTTL
Clock for Activity Monitor, <10MHz.
ACTIVITY
ALE_SCN
Activity Result from Previous ACTCLK Period
AD25
Address Latch Enable for Multiplexed Parallel Mode; Scan Enable
for Serial Mode. See Figure 1 through Figure 4 for proper use.
CMV
AD3
F27
AF6
AD4
Analog
LVTTL
LVTTL
TTL
Output Drive Current Control. Leave floating.
CONFIG
CS
Logic HIGH Transfers Programming to Main Program Memory
Chip Select, Active LOW. Selects between multiple devices.
Output Drive Current Switch. LOW = 10mA, HIGH = 20mA.
DRIVE_CTRL
13 of 19
VMDS-10195 Revision 4.0
August 19, 2005
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
