VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
OC-48 16:1 SONET/SDH
MUX with Clock Generator
VSC8163
AC Characteristics
Figure 9: Parallel Input Data and Clock Timing Waveforms
CLK16I+
Parallel Data Clock Input
tTXDSU
tTXDH
D[0...15]+
Parallel Data Inputs
Valid Data 1
Valid Data 2
CLK16O+
Parallel Data Clock Output
= don't care
Figure 10: Serial Data and Clock Output Phase Timing Waveforms
CLKOPER
DO+
D13
D1
D0
D15
D14
Differential Serial Data Output
LSB
MSB
tSET
Time
CLKO+
Differential Clock Output
tHOLD
NOTE: Bit 15 (MSB) is received first, Bit 0 (LSB) is received last.
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52216-0, Rev 3.3
01/05/01
Page 7
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
