VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
OC-48 16:1 SONET/SDH
MUX with Clock Generator
VSC8163
Figure 2: Enabling FIFO Operation
PLL locked to reference clock.
FIFO Mode Operation
Transparent Mode Operation
Minimum 5 CLK16 cycles (32ns)
RESET
Holding RESET “low” for a minimum of five CLK16 cycles, then setting “high” enables FIFO operation.
Holding RESET constantly “low” bypasses the FIFO for transparent mode operation.
Figure 3: Split-End DC Termination of CLK16O+/-, REFCLKO+/-
VCC
Split-end equivalent termination is Z0 to VTERM
R1 = 125Ω R2 = 83Ω, Zo=50Ω, VTERM= VCC-2V
R1
R2
R1
VSC8163
Zo
Zo
R1||R2 = Z0
R2
VCCR2 + VEER1
= VTERM
R1+R2
VEE
Figure 4: Traditional DC Termination of CLK16O+/-, REFCLKO+/-
VSC8163
Z0
Z0
50Ω
50Ω
VCC-2V
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52216-0, Rev 3.3
01/05/01
Page 3
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
