VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
OC-48 16:1 SONET/SDH
MUX with Clock Generator
VSC8163
Figure 5: AC Termination of CLK16O+/-, REFCLKO+/-
VSC8163
downstream
Z0
Z0
100nF
bias point
generated
internally
100nF
50Ω
VCC-2V
50Ω
High-Speed Data and Clock Output
The high-speed data and clock output drivers consist of a differential pair designed to drive a 50Ω transmis-
sion line. The transmission line should be terminated with a 100Ω resistor at the load between true and comple-
ment outputs (see Figure 6). Connection to a termination voltage is not required. The output driver is back
terminated to 50Ω on-chip, providing a snubbing of any reflections. If used single-ended, the high-speed output
driver must still be terminated differentially at the load with a 100Ω resistor between true and complement out-
puts. The high-speed clock output can be powered down for additional power savings. To power down the high-
speed clock, tie the associated pins to V (see Table 3, Package Pin Descriptions, pins 5,6,7).
CC
Figure 6: High-Speed Output Termination
VCC
50Ω
50Ω
100Ω
Z0 = 50Ω
Pre-Driver
VEE
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 4
G52216-0, Rev 3.3
01/05/00
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
