VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC8163
b
a
b
a
Single
Ended
Swing
OC-48 16:1 SONET/SDH
MUX with Clock Generator
Figure 11: Differential and Single-Ended Input / Output Voltage Measurement
=
α
Differential
Swing
=
α
* Differential swing
(α)
is specified as | b - a | ( or | a - b | ), as is the single ended swing.
Differential swing is specified as equal in magnitude to single ended swing.
Table 2: DC Characteristics
(Over recommended operating conditions)
Parameters
V
OH(DO)
V
OL(DO)
∆V
OD(DO)
∆V
OCLK(CLKO)
V
CMO
R
DO
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
R
I
∆V
I
V
CMI
V
OH
V
OL
V
IH
Description
Output HIGH voltage (DO)
Output LOW voltage (DO)
Data output differential voltage
(DO)
CLK output differential voltage
(CLKO)
Output common-mode voltage
Back termination impedance
Output HIGH voltage
(CLK16O, REFCLKO)
Output LOW voltage
(CLK16O, REFCLKO)
Input HIGH voltage (LVPECL)
Input LOW voltage (LVPECL)
Input HIGH current (LVPECL)
Input LOW current (LVPECL)
Input resistance (LVPECL)
Input differential voltage
(LVPECL)
Input common-mode voltage
(LVPECL)
Output HIGH voltage (TTL)
Output LOW voltage (TTL)
Input HIGH voltage (TTL)
Min
V
CC
- 0.825
V
CC
- 1.30
550
500
2.10
40
V
CC
- 1.020
V
CC
- 2.000
V
CC
- 1.100
V
CC
- 2.0
—
-50
10k
200
V
CC
- 1.5
2.4
—
2.0
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
V
CC
V
CC
- 0.50
900
900
3.00
60
V
CC
- 0.700
V
CC
- 1.620
V
CC
- 0.700
V
CC
- 1.540
200
—
—
—
V
CC
- 0.5
—
0.5
5.5
Units
V
V
mV
mV
V
Ω
V
V
V
V
µA
µA
Ω
mV
V
V
V
V
Conditions
See Figure 12
See Figure 12
100Ω termination
between DO± at load
100Ω termination
between DO± at load
Guaranteed, not tested
See Figure 12
See Figure 12
V
IN
=V
IH
(max)
V
IN
=V
IL
(min)
I
OH
= -1.0mA
I
OL
= +1.0mA
G52216-0, Rev 3.3
01/05/01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 9
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
