VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
OC-48 16:1 SONET/SDH
MUX with Clock Generator
VSC8163
Table 1: AC Characteristics
Parameters
Description
Min
Typ
Max Units
Conditions
Data setup time to the rising
edge of CLK16I+
TDSU
0.75
—
—
—
ns
ns
ps
Data hold time after the
rising edge of CLK16+
TDH
1.0
—
—
20% to 80% into 100Ω load
See Figure 6
TDOR,TDOF
DO± rise and fall time
—
120
tCLKR, tCLKF
CLK16OD
CLKID
CLK16O± rise and fall times
CLK16O± duty cycle
CLK16I± duty cycle
—
40
30
40
40
—
—
—
—
—
250
60
ps
%
%
%
%
See Figures 3 and 4
70
Assuming 10% distortion of CLKO
RCKD
Reference clock duty cycle
CLKO duty cycle
60
CLKOD
60
SONET based 77.76MHz or
155.52MHz reference clock
CLKOPER
CLK16OPER
tSET
CLKO period
—
—
—
—
401.9
6.4
—
—
—
—
ps
ns
ps
ps
SONET based 77.76MHz or
155.52MHz reference clock
CLK16O period
DO setup time with respect
to rising CLKO edge
Inverting CLKO will switch (approx)
90
t
SET and tHOLD values.
DO hold time with respect to
rising CLKO edge
Inverting CLKO will switch (approx)
tSET and tHOLD values.
tHOLD
310
Clock Multiplier Performance
rms, tested to SONET specification
(12kHz to 20MHz) with 2ps rms jitter
on REFCLK.
TDJ
Output data jitter
Output clock jitter
—
—
—
4
4
ps
ps
rms, tested to SONET specification
(12kHz to 20MHz) with 2ps rms jitter
on REFCLK.
TCJ
—
—
Jittertol
Jitter tolerance
Tuning Range
—
—
—
Exceeds SONET/SDH mask
-100
+100
ppm
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 8
G52216-0, Rev 3.3
01/05/00
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
