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VSC8140TW 参数 Datasheet PDF下载

VSC8140TW图片预览
型号: VSC8140TW
PDF下载: 下载PDF文件 查看货源
内容描述: 2.48832Gb / s的16 : 1 SONET / SDH收发器,集成时钟发生器 [2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator]
分类和应用: 时钟发生器ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 34 页 / 530 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
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VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8140
Features
• 2.48832Gb/s 16-Bit Transceiver
• Targeted for SONET OC-48 / SDH STM-16
Applications
• LVPECL Low-Speed Interface
• On-chip PLL-Based Clock Generator
• High-Speed Clock Output With Power-Down
Option
• Supports Parity at the 16-Bit Parallel Transmit
and Receive Interfaces
2.48832Gb/s 16:1 SONET/SDH
Transceiver with Integrated Clock Generator
• Provides Equipment, Facilities and Split Loop-
back Modes as well as Loop Timing Modes
• Loss of Signal (LOS) Detect input
• Meets Bellcore Jitter Performance Specifications
• Single +3.3V Supply
• 2.25 Watts Typical Power Dissipation
• Packages: 128-pin PQFP or 208-pin TBGA
General Description
The VSC8140 is a SONET/SDH compatible transceiver with integrated clock generator for use in SONET/
SDH systems operating at a 2.48832Gb/s data rate. The internal clock generator uses a Phase-Locked Loop
(PLL) to multiply either a 77.76MHz or 155.52MHz reference clock in order to provide the 2.48832GHz clock
for internal logic and output retiming. The 16-bit parallel interface incorporates an on-board FIFO eliminating
loop timing design issues by providing a flexible parallel timing architecture. In addition, the device provides
both facility and equipment loopback modes and two loop timing modes. The VSC8140 operates using a 3.3V
power supply, and is available in either a thermally-enhanced 128-PQFP or a thermally-enhanced 208-pin
TBGA package.
VSC8140 Block Diagram
LOS
POL
RXIN+
RXIN-
RXCLKIN+
RXCLKIN-
D Q
voltage
gen.
Output Register
VREFOUT
VREFIN
RXOUT0
RXOUT15
RXPARITYOUT
RXCLK16O+
RXCLK16O-
EQULOOP
CLK128O+
CLK128O-
RXCLKO_FREQSEL
OVERFLOW
FIFORESET
TXOUT+
TXOUT-
TXCLKOUT+
TXCLKOUT-
FACLOOP
Q D
Divide
by 128
Divide by
16
Divide by
2
RXCLKO16_32+
RXCLKO16_32-
PARMODE
TXCLK16I+
TXCLK16I-
Input Register
TXIN0
Write
Pointer
FIFO
CNTRL
16x5 FIFO
TXIN15
TXPARITYIN
Read
Pointer
Divide by
16
TXCLK16O+
TXCLK16O-
LPTIMCLK+
LPTIMCLK-
LOOPTIM0
2.48832GHz
PLL
PARERR
REFCLK+
REFCLK-
LOOPTIM1
REF_FREQSEL
G52251-0, Rev. 4.0
9/6/00
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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