VSC8113
Data Sheet
F
UNCTIONAL
D
ESCRIPTION
The VSC8113 is designed to provide a SONET/SDH-compliant interface between the high-speed optical networks
and the lower speed User Network Interface devices such as the PM5355 S/UNI-622. The VSC8113 converts 8-bit
parallel data at 77.76Mb/s or 19Mb/s to a serial bit stream at 622.08Mb/s or 155.52Mb/s, respectively. The VSC8113
also provides a Facility Loopback function which loops the received high-speed data and clock (optionally recovered
on-chip) directly to the high-speed transmit outputs. A Clock Multiplier Unit (CMU) is integrated into the transmit
circuit to generate the high-speed clock for the serial output data stream from input reference frequencies of 19.44,
38.88, 51.84 or 77.76 MHz. The CMU can be bypassed with the received/recovered clock in loop timing mode thus
synchronizing the entire part to a single clock. See the Block Diagram for major functional blocks associated with the
VSC8113.
The receive section provides the serial-to-parallel conversion, converting the 622Mb/s or 1.55.52Mb/s bit stream to an
8-bit parallel output at 19.44Mb/s or 77.76MHz, respectively. A Clock Recovery Unit (CRU) is integrated into the
receive circuit to recover the high-speed clock from the received serial data stream. The receive section provides an
Equipment Loopback function which will loop the low-speed transmit data and clock back through the receive
section to the 8-bit parallel data bus and clock outputs.The VSC8113 also provides the option of selecting between
either its internal CRU’s recovered clock and data signals or optics containing a CRU clock and data signals. (In this
mode the VSC8113 operates just like the VSC8111). The receive section also contains a SONET/SDH frame detector
circuit which is used to provide frame pluses during the A1, A2 boundary in the serial to parallel converter. This only
occurs when OOF is HIGH. Both internal and external LOS functions are supported.
Transmit Section
Byte-wide data is presented to TXIN[7:0] and is clocked into the part on the rising edge of TXLSCKIN. See Figure 1.
The data is then serialized (MSB leading) and presented at the TXDATAOUT+/- pins. TXDATAOUT is clocked out
on the falling edge of TXCLKOUT+. The serial output stream is synchronized to the CMU generated clock which is
a phase-locked and frequency scaled version of the input reference clock. External control inputs B0-B2 and STS-12
select the multiply ratio of the CMU for either STS-12 (622Mb/s) or STS-3 (155MbS) transmission (see Table 12). A
divide-by-8 version of the CMU clock (TXLSCKOUT) should be used to synchronize the transmit interface of the
UNI device to the transmit input registers on the VSC8113 (see
Interconnecting the Byte Clocks
section).
VSC8113
PM5355
TXDATAOUT+
TXDATAOUT-
TXCLKOUT+
TXCLKOUT-
Q D
Q D
TXIN[7:0]
Q D
TXLSCKIN
REFCLK
CMU
Divide-by-8
TXLSCKOUT
Figure 1. Data and Clock Transmit Block Diagram
3 of 22
G52154, Rev 4.5
6/28/02
Confidential
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
