VSC7216-02
Data Sheet
Notation
In this document, each of the four channels are identified as channel A, B, C or D. When discussing a signal on any
specific channel, the signal will have the channel letter embedded in the name, for example, TA[7:0]. When referring
to the common behavior of a signal that is used on each of the four channels, a lower case “n” is used in the signal
name, for example, Tn[7:0]. Differential signals (for example, PTXA+ and PTXA-), may be referred to as a single
signal (for example, PTXA), by dropping reference to the + and -. REFCLK refers to either the PECL/TTL input pair
REFCLKP/REFCLKN, which can be differential PECL (using both REFCLKP and REFCLKN), or single-ended
TTL (using REFCLKP and leaving REFCLKN open).
Clock Synthesizer
Depending on the state of the DUAL input, the VSC7216-02 clock synthesizer multiplies the reference frequency
provided on the REFCLK input by 10 (DUAL is LOW) or 20 (DUAL is HIGH) to achieve a baud rate clock between
0.98GHz and 1.36GHz. The on-chip Phase-Locked Loop (PLL) uses three external 0.1µF capacitors; one connected
between CAP0 and CAP1, and two capacitors to ground, to control the Loop Filter. If a three-capacitor circuit cannot
be used, a single differential capacitor is adequate (see
C in Figure 1). These capacitors should be of multilayer
1
ceramic dielectric, or better, with at least a 5V working voltage rating and a good temperature coefficient (NPO is
preferred but X7R may be acceptable). These capacitors are used to minimize the impact of common-mode noise on
the Clock Multiplier Unit (CMU), especially power supply noise. Higher value capacitors provide better robustness in
systems. NPO is preferred because if an X7R capacitor is used, the power supply noise sensitivity will vary with
temperature. Larger values are better but 0.1µF is adequate. These components should be isolated from noisy traces.
C1 = C2 = C3 = >0.1µF
Multilayer Ceramic
C2
C3
CAP0
CAP1
C1
Surface Mount
VSC7216-02
NPO (preferred) or X7R
5V Working Voltage Rating
Figure 1. Loop Filter Capacitors (best circuit)
The REFCLK signal can be either single-ended TTL or differential LVPECL. If TTL, connect the TTL input to
REFCLKP and terminate REFCLKN as shown in Figure 25 on page 27. If LVPECL, connect the inputs to
REFCLKP and REFCLKN. Internal biasing resistors sets the proper DC Level to V /2.
DD
Serial and parallel data rates for all channels may be halved by means of the RATE pin. When RATE is HIGH, the
chip is in full-speed mode (default mode of operation), and when LOW, the half-speed mode is selected. Table 1
shows the interaction of the DUAL and RATE inputs.
Table 1. Using the RATE Input to Achieve Half-Speed Operation
ClockMultiplication
RATE Pin
DUAL Pin
Factor
Serial Link Speed Parallel Data Rate
REFCLK Frequency
50MHz
0
0
1
1
0
1
0
1
x10
500Mb/s
500Mb/s
1Gb/s
50Mb/s
50Mb/s
x20
25MHz
x10
100Mb/s
100Mb/s
100MHz
x20
1Gb/s
50MHz
3 of 40
G52367 Revision 4.2
December 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
