VSC7216-02
Data Sheet
Transmitter
Receiver
10
Clk/Data
Recovery
PSDETD
RSDETD
10
3
Clk/Data
Recovery
PSDETC
RSDETC
10
Clk/Data
Recovery
PSDETB
RSDETB
10
Clk/Data
Recovery
PSDETA
RSDETA
8
3
8B/10B
8B/10B
Decode
Decode
RXFIFO[1:0]
8
8
8B/10B
Decode
3
Elastic
Buffer
RXFIFO[1:0]
8
Elastic
Buffer
8
Elastic
Buffer
8
8B/10B
Decode
RXFIFO[1:0]
8B/10B
Decode
3
Elastic
Buffer
8
8
PTXEND
8
8B/10B
Encode
10
RTXEND
PTXENC
8
8B/10B
Encode
RTXENC
PTXENB
8
8B/10B
Encode
10
RTXENB
PTXENA
8
8B/10B
Encode
10
RTXENA
10
8
TD[7:0]
C/DD
WSEND
D Q
LBEND[1:0]
RXP/RD
LBTXD
RREF
PTXD+ PRXD+
PTXD- PRXD-
RTXD+ RRXD+
RTXD- RRXD-
RD[7:0]
IDLED
KCHD
ERRD
RCLKD
RCLKDN
8
VSC7216-02 Block Diagram
RC7:0)
IDLEC
KCHC
ERRC
RCLKC
RCLKCN
TC[7:0]
C/DC
WSENC
D Q
LBENC[1:0]
RXP/RC
LBTXC
RREF
PTXC+ PRXC+
PTXC- PRXC-
RTXC+ RRXC+
RTXC- RRXC-
8
TB[7:0]
C/DB
WSENB
2 of 40
LBENA[1:0]
RXP/RA
LBTXA
RREF
PTXA+ PRXA+
PTXA- PRXA-
RTXA+ RRXA+
RTXA- RRXA-
4
Tx Clock
REFCLK
TMODE(2:0)
RMODE[1:0]
TBERRA
TBERRB
TBERRC
TBERRD
RESETN
ENDEC
BIST
CREG
D Q
LBENB[1:0]
RXP/RB
LBTXB
RREF
PTXB+ PRXB+
PTXB- PRXB-
RTXB+ RRXB+
RTXB- RRXB-
RB[7:0]
IDLEB
KCHB
ERRB
RCLKB
RCLKBN
8
TA[7:0]
C/DA
WSENA
D Q
RA[7:0]
IDLEA
KCHA
ERRD
RXFIFO[1:0]
WSI
FLOCK
Channel
Align
RCLKA
RCLKAN
WSO
KCHAR
x20/x10
Clock Gen
JTAG
Boundary
Scan
TDO
TBCA
TBCB
TBCC
TBCD
DUAL
RATE
REFCLKP
REFCLKN
CAP0 CAP1
TRSTN
TMS
TDI
TCK
Downloaded by pm_virendrakumar@yahoo.com on February 14, 2007 from Vitesse.com
G52367 Revision 4.2
December 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
