VSC7216-02
Data Sheet
Internal Voltage Regulator
There is a voltage regulator on-chip that requires an external capacitance of at least 4.7μF attached from its output,
CREG, to GND. A capacitor value of 10μF is recommended.
Analog Power Supply Considerations
The VSC7216-02 contains an internal PLL that is powered by separate analog power supply pins denoted as VDDA/
VSSA. The performance of the VSC7216-02 is particularly sensitive to noise on these pins, therefore, special care
should be taken to filter out any such noise. It is recommended that V pass through a ferrite bead and onto the
DD
V
pin, which should be bypassed with a pair of 0.1µF and 10µF capacitors.
DDA
TRANSMITTER FUNCTIONAL DESCRIPTION
Transmitter Data Bus
Each VSC7216-02 transmit channel has an 8-bit input transmit data character, Tn[7:0], and two control inputs, C/Dn
and WSENn. The C/Dn input determines whether a normal data character or a special K-character is transmitted, and
the WSENn input initiates transmission of a 16-character “Word Sync Sequence” used to align the receive channels.
These data and control inputs are clocked either on the rising edge of REFCLK, on the rising edge of TBCn, or within
the data eye formed by TBCn. When not using REFCLK, each channel uses either its own TBCn input, or uses the
TBCA input. The transmit interface mode is controlled by TMODE[2:0] as shown in Table 2.
When used, the TBCn inputs must be frequency-locked to REFCLK. No phase relationship is assumed. A small skew
buffer is provided to tolerate phase drift between TBCn and REFCLK. This buffer is recentered by the RESETN
input, and the total phase drift after recentering must be limited to +/- 180° (where 360° is one character time). Each
channel has an error output, TBERRn, that is asserted HIGH to indicate that the phase drift between TBCn and
REFCLK has accumulated to the point that the elastic limit of the skew buffer has been exceeded and a transmit data
character has been either dropped or duplicated. This error can not occur when input timing is referenced to
REFCLK. The TBERRn output timing is identical to the low-speed receiver outputs, as selected by RMODE[1:0] in
Table 6 on page 11.
Table 2. Transmit Interface Input Timing Mode
TMODE[2:0]
Input Timing Reference
0 0 0
REFCLK Rising Edge
0 0 1
0 1 0
0 1 1
Reserved
1 0 0
1 0 1
1 1 0
1 1 1
TBCA Rising Edge
TBCn Rising Edge
TBCA Data Eye
TBCn Data Eye
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G52367 Revision 4.2
December 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
