VSC7216-02
Data Sheet
This package uses an industry-standard footprint. The package construction is shown in Figure 29.
Copper Heat Spreader
Die
Wirebond
Die Attach Epoxy
Adhesive
Polyimide Dielectric
Encapsulant
Eutectic Solder Balls
Figure 29. Package Cross Section
Thermal Specifications
Thermal specifications for this device are based on the JEDEC standard EIA/JESD51-2 and have been modeled using
a four-layer test board with two signal layers, a power plane, and a ground plane (2s2p PCB). For more information,
see the JEDEC standard.
Table 24. Thermal Resistances
θ
JA (°C/W) vs. Airflow (ft/min)
θJC
Part Order Number
VSC7216UC-02
VSC7216XUC-02
VSC7216UI-02
0
100
11
11
11
200
0.7
0.7
0.7
0.7
14.4
14.4
14.4
14.4
9.3
9.3
9.3
9.3
VSC7216XUI-02
11
To achieve results similar to the modeled thermal resistance measurements, the guidelines for board design described
in the JEDEC standard EIA/JESD51 series must be applied. For information about specific applications, see the
following:
EIA/JESD51-5, Extension of Thermal Test Board Standards for Packages with Direct Thermal Attachment
Mechanisms
EIA/JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
EIA/JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
EIA/JESD51-10, Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements
EIA/JESD51-11, Test Boards for Through-Hole Area Array Leaded Package Thermal Measurements
38 of 40
G52367 Revision 4.2
December 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
