VITESSE
SEMICONDUCTOR CORPORATION
Quad Transceiver
for Gigabit Ethernet
Advance Product Information
VSC7186
Figure 4: Receive Timing Waveforms
RCi0
RCM=LOW
RCi1
RCi0
RCM=HIGH
RCi1
T
1
T
2
VALID
VALID
RXi(0:9)
SYNi
VALID
+/-SIi
S0
S1
S2
R
LAT
RCi1
Table 3: Receive AC Characteristics
—
Parameters
T
1
T
2
T
3
T
4
T
R
, T
F
T
LOCK
Description
TTL Outputs Valid prior to
RCi1/RCi0 rise
TTL Outputs Valid after
RCi1 or RCi0 rise
Delay between rising edge of
RCi1 to rising edge of RCi0
Period of RCi1 and RCi0
TTL Output rise and fall
time
Data acquisition lock time*
Latency from bit 0 of RXi0
appearing on SI to rising
edge of RCi1
Min.
3.0
2.0
10 x T
Ri
-500
1.98 x T
REF
—
—
12bc +
2.77ns
Max.
—
—
10 x T
Ri
+500
2.02 x T
REF
2.4
1400
13bc +
7.28
Units
ns.
ns.
ps.
ps.
ns.
bit
times
Note:
Conditions
@ 1.25Gb/s
@ 1.25Gb/s
T
Ri
is the bit period of the
incoming data on Ri.
Whether or not locked to
serial data.
Between V
IL(max)
and
V
IH(min)
, into 10 pf. load.
8b/10b IDLE pattern.
Tested on a sample basis
bc = bit clocks
ns = nanoseconds.
R
LAT
* Note: Probability of recovery for data acquisition is 95% per Section 5.3 of FC-PH rev. 4.3
Page 6
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52306-0, Rev. 2.0
3/27/00
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
