VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
1.25Gbits/sec
Gigabit Ethernet Transceiver
VSC7135
Figure 5: Receive Timing Waveforms
T
4
T
3
RCLK
RCLKN
T
T
2
1
Data Valid
Data Valid
Data Valid
R0:9
Table 2: Receive AC Characteristics
Parameters
Description
Min.
Max.
Units
Conditions
Data or COM_DET Valid
prior to RCLK/RCLKN
rise
3.0
—
ns.
T
Measured between the 1.4V
point of RCLK or RCLKN
and a valid level of R0:9. All
outputs driving 10pF load.
1
Data or COM_DET Valid
after RCLK or RCLKN
rise
2.0
—
ns.
ps.
T
2
3
Deviation of RCLK
rising edge to RCLKN
rising edge delay from
nominal.
Nominal delay is 10 bit times.
Tested on sample basis
-500
500
T
f baud
delay= ------------- ± T 3
10
Deviation of RCLK,
RCLKN frequency from
nominal.
Whether or not locked to
serial data
-1.0
1.0
%
T
4
f REFCLK
f RCLK= ---------------------- ± T 4
2
R0:9, COM_DET, RCLK,
RCLKN rise and fall time
Between V
into 10 pf. load.
and V
,
il(max)
ih(min)
—
15bc + 2ns
—
2.4
34bc + 2ns
2.0
ns.
T , T
R
F
bc = Bit clock
ns = Nano second
R
Latency from RX to R0:9
lat
Data acquisition lock time
@ 1.25 Gb/s
8B/10B IDLE pattern.
Tested on a sample basis
µs.
ps
T
LOCK
Total receive data jitter
tolerance (p-p)
IEEE 802.3Z Clause 38.68,
tested on a sample basis
599
T
jtd
Total deterministic data
jitter tolerance (p-p)
IEEE 802.3Z Clause 38.69,
tested on a sample basis
370
ps
D
jtd
NOTE: Probability of Recovery for data acquisition is 95% per section 5.3 of the FC-PH rev. 4.3.
Page 6
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52146-0, Rev. 4.0
5/28/98
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
