VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
1.25Gbits/sec
Gigabit Ethernet Transceiver
VSC7135
Functional Description
Clock Synthesizer
The VSC7135 clock synthesizer multiplies the reference frequency provided on the REFCLK pin by 10 to
achieve a baud rate clock at nominally 1.25GHz. The clock synthesizer contains a fully monolithic PLL which
does not require any external components.
Serializer
The VSC7135 accepts TTL input data as a parallel 10 bit character on the T0:9 bus which is latched into the
input latch on the rising edge of REFCLK. This data will be serialized and transmitted on the TX PECL differ-
ential outputs at a baud rate of ten times the frequency of the REFCLK input, with bit T0 transmitted first. User
data should be encoded for transmission using the 8B/10B block code described in the Fibre Channel specifica-
tion, or an equivalent, edge rich, DC-balanced code.
Transmission Character Interface
An encoded byte is 10 bits and is referred to as a transmission character. The 10 bit interface on the
VSC7135 corresponds to a transmission character. This mapping is illustrated in Figure 2.
Figure 1: Transmission Order and Mapping of an 8B/10B Character
Parallel Data Bits
8B/10B Bit Position
Comma Character
T9 T8 T7 T6 T5 T4 T3 T2 T1 T0
j
h
g
f
i
e
d
1
c
b
0
a
X
X
X
1
1
1
1
0
First Data Bit Transmitted
Last Data Bit Transmitted
Clock Recovery
The VSC7135 accepts differential high speed serial inputs on the RX+/RX- pins, extracts the clock and
retimes the data. The serial bit stream should be encoded so as to provide DC balance and limited run length by
an 8B/10B transmitter or equivalent. The VSC7135 clock recovery circuitry is completely monolithic and
requires no external components. For proper operation, the baud rate of the data stream to be recovered should
be within 0.01% of ten times the REFCLK frequency. For example if the REFCLK used is 125MHz, then the
incoming serial baud rate must be 1.25 gigabaud +0.01%.
Deserializer
The retimed serial bit stream is converted into a 10-bit parallel output character. The VSC7135 provides
complementary TTL recovered clocks, RCLK and RCLKN, which are at one-twentieth of the serial baud rate.
This architecture is designed to simplify demultiplexing of the 10-bit data characters into a 20-bit half-word in
the downstream controller chip. The clocks are generated by dividing down the high-speed clock which is phase
locked to the serial data. The serial data is retimed by the internal high-speed clock, and deserialized. The result-
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VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52146-0, Rev. 4.0
5/28/98
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
