VSC7123
Datasheet
Signal Detection
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The receiver has an output, SIGDET, indicating, when HIGH, that the RX input contains a valid Fibre Channel or
Gigabit Ethernet signal. A combination of one analog and three digital checks are used to determine if the incoming
signal contains valid data. SIGDET is updated every four RCLKs. If during the current period, all four criteria are
met, SIGDET will be HIGH during the next four RCLK periods. If during the current period, any of the four criteria
is not met, SIGDET will be LOW during the next four RCLK periods.
1. Analog transition detection is performed on the input to verify that the signal swings are of adequate
amplitude. The RX± input buffer contains a differential voltage comparator which goes HIGH if the
differential peak-to-peak amplitude is greater than 400 mV or LOW if under 200 mV. If the amplitude is
between 200 mV and 400 mV, the output is indeterminate.
2. Data on R(0:9) is monitored for all zeros (0000000000). If this pattern is encountered during the current RCLK
interval, the SIGDET output goes LOW during the next four RCLK intervals.
3. Data on R(0:9) is monitored for all ones (1111111111). If this pattern is encountered during the current RCLK
interval, the SIGDET output goes LOW during the next four RCLK intervals.
4. Data on R(0:9) is monitored for K28.5– (0011111010). Unlike previous patterns, the interval during which a
K28.5– must occur is 64 K + 24 10-bit characters in length. Valid Fibre Channel or Gigabit Ethernet data
contains a K28.5– character during any period of this length. If a K28.5– character is not detected during the
monitoring period, SIGDET goes LOW during the next period.
The behavior of SIGDET is affected by EWRAP and ENCDET, as shown in
Note that COMDET, RCLK,
RCLKN, and R(0:9) are unaltered by SIGDET.
Table 1. Signal Detect Behavior
EWRAP
0
0
1
1
ENCDET
0
1
0
1
COMDET
Disabled
Enabled
Disabled
Enabled
Transition
Detect
Enabled
Enabled
Enabled
Enabled
All Zeros/
All Ones
Enabled
Enabled
Disabled
Disabled
K28.5
Presence
Enabled
Disabled
Disabled
Disabled
Mode
Normal
SIGDET ignores commas
Rollback
Loopback
JTAG Access Port
A JTAG Access Port is provided to assist in board-level testing. Through this port, most pins can be accessed or
controlled and all TTL outputs can be tri-stated.
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G52212-0 Revision 4.7
March 14, 2008
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
