VSC7123
Datasheet
Electrical Specifications
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AC Characteristics
Specifications listed in the following tables are guaranteed over the recommended operating conditions listed in
unless otherwise noted.
Figure 4. Transmit Timing Waveforms
REFCLK
T
1
T
2
T(0:9)
Data Valid
Data Valid
Data Valid
Table 2. Transmit AC Characteristics
Symbol
T
1
Parameter
T(0:9) Setup time to the rising
edge of REFCLK
T(0:9) hold time after the
rising edge of REFCLK
TX+/TX– rise and fall time
Latency from rising edge of
REFCLK to T0 appearing on
TX+/TX–
Random jitter (RMS)
8bc
Minimum
1.5
Typical
Maximum
Unit
ns
Condition
Measured between the valid
data level of T(0:9) to the 1.4 V
point of REFCLK.
T
2
T
SDR
,T
SDF
T
LAT
1.0
300
8bc + 4 ns
ns
ps
ns
20% to 80%, 50
Ω
load to
V
DD
– 2.0.
bc = Bit clocks
ns = Nanosecond
Transmitter Output Jitter Allocation
RJ
5
8
ps
Measured at SO±, 1 sigma
deviation of 50% crossing
point.
IEEE 802.3Z Clause 38.68,
tested on a sample basis.
DJ
Serial data output
deterministic jitter (p-p)
30
80
ps
6 of 22
G52212-0 Revision 4.7
March 14, 2008
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
