VSC7123
Datasheet
Figure 5. Receive Timing Waveforms
T4
RCLK
T
3
RCLKN
T2
T1
Data Valid
Data Valid
Data Valid
R(0:9)
Table 3. Receive AC Characteristics
Symbol
Parameter
Minimum
Maximum
Unit
Condition
At 1.0625 Gbps
At 1.25 Gbps
T1
TTL Outputs Valid prior to
RCLK/RCLKN rise
4.0
3.0
ns
T2
T3
TTL Outputs Valid after RCLK
or RCLKN rise
3.0
ns
ps
At 1.0625 Gbps
At 1.25 Gbps
2.0
Delay between rising edge of
RCLK to rising edge of
RCLKN
10 x TRX
–500
10 x TRX
+500
TRX is the bit period of the
incoming data on Rx.
T4
Period of RCLK and RCLKN
1.98 x TREFCLK
2.02 x TREFCLK
2.4
ps
ns
Whether or not locked to
serial data.
TR, TF
R(0:9), COMDET, SIGDET,
RCLK and RCLKN rise and
fall time
Between VIL(MAX) and
VIH(MIN), into 10 pF load.
RLAT
Latency from RX to R(0:9)
12 bc + 1 ns
13 bc + 9 ns
1400
bc
ns
bc
bc = bit clocks
ns = nanoseconds
(1)
TLOCK
Data acquisition lock time
8b/10b pattern.
bc = bit clocks
1. Probability of recovery for data acquisition is 95% per Section 5.3 of FC-PH revision 4.3.
7 of 22
G52212-0 Revision 4.7
March 14, 2008
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
