VSC7123
Datasheet
Downloaded by data_acq@partminer.com on September 22, 2009 from Vitesse.com
10-Bit Transceiver for Fibre Channel and Gigabit Ethernet
Features
●
●
●
●
802.3z Gigabit Ethernet-compliant
1.25 Gbps transceiver
ANSI X3T11 Fibre Channel-compliant
1.0625 Gbps transceiver
0.98 to 1.36 Gbps full-duplex operation
10-Bit TTL interface for transmit and receive data
●
●
●
●
●
●
Automatic lock-to-reference
RX cable equalization
Analog and digital signal detection
JTAG access port for testability
Single +3.3 V supply, 650 mW typical
Packages: 64-pin 10 mm and 14 mm QFP and
10 mm and 14 mm TQFP
General Description
The VSC7123 is a full-speed Fibre Channel and Gigabit Ethernet transceiver with industry-standard pinouts. The
VSC7123 accepts 10-bit 8B/10B encoded transmit data, latches it on the rising edge of REFCLK and serializes the
data onto the TX PECL differential outputs at a baud rate, which is 10 times the REFCLK frequency. Serial data input
on the RX PECL differential inputs is resampled by the Clock Recovery Unit (CRU) and deserialized onto the 10-bit
receive data bus synchronously to complementary divide-by-twenty clocks. The VSC7123 receiver detects “Comma”
characters for frame alignment. An analog/digital signal detection circuit indicates that a valid signal is present on the
RX input. A cable equalizer compensates for InterSymbol Interference (ISI) to increase maximum cable distances.
The VSC7123 is a higher performance, lower cost replacement for the VSC7125 and VSC7135.
Block Diagram
R(0:9)
10
QD
Serial to
Q Parallel D
÷10
QD
2:1
RX+
RX-
RCLK
RCLKN
COMDET
ENCDET
EWRAP
SIGDET
T(0:9)
10
Clock
Recovery
÷20
Comma
Detect
Signal
Detect
Parallel
to Serial
DQ
DQ
TX+
TX-
REFCLK
x10 Clock
Multiply
NOT SHOWN: JTAG Boundary Scan
G52212-0 Revision 4.7
March 14, 2008
©
VITESSE SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • E-mail: webmaster@vitesse.com
Internet: www.vitesse.com
1 of 22
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
