Advance Product Information
Subject to Change
VSC7111 Datasheet
Registers
Table 40.
Register 60’h: Input AEQ Control (continued)
Bit Name
Access Description
R/W Input AEQ short/long ratio control
Default
5:3 GAEQSLRATIO
100
111: 7:1
110: 6:1
101: 5:1
100: 4:1
011: 3.5:1
010: 3:1
001: 2.5:1
000: 2:1
2:0 GAEQGOAL
R/W
Input AEQ goal control
111: 81:64
100
110: 78:64
101: 75:64
100: 72:64
011: 69:64
010: 66:64
001: 63:64
000: 60:64
3.4.16
Reserved
This register is for Vitesse use only.
Table 41.
Register 6D’h: Reserved
Bit Name
Access Description
Default
7:0 Reserved
R
Reserved. Vitesse use only. All zeros
3.4.17
Reserved
This register is for Vitesse use only.
Table 42.
Register 6F’h: Reserved
Bit Name
Access Description
Default
0000
7:4 Reserved
3:0 Reserved
R
Reserved. Vitesse use only.
Reserved. Vitesse use only.
R/W
0000
3.4.18
Rx Detect Delay 0
This register sets the delay before first sample for PCI-E receive detect in units of
250 ns.
Table 43.
Register 76’h: Rx Detect Delay0
Bit Name
Access Description
Default
7:0 RXDETDEL0
R/W
Delay value
08'h (2 µs)
0–255: Delay of sample time in units of 250 ns
Revision 2.0
September 2010
Confidential
Page 41
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
