Advance Product Information
Subject to Change
VSC7111 Datasheet
Registers
3.4.19
Rx Detect Delay 1
This register sets the delay before second sample for PCI-E receive detect in units of
4 µs.
Table 44.
Register 77’h: Rx Detect Delay
Bit Name
Access Description
Default
7:0 RXDETDEL1
R/W
Delay value
05'h (20 µs)
0–255: Delay of sample time in units of 4 µs
3.4.20
Serial Address
This register sets the two-wire serial address.
Table 45.
Register 78’h: Serial Address
Bit Name
Access Description
Default
7
Reserved
R/W
R/W
Reserved
0
6:0 SERADDR
Two-wire serial address
0000000
1111111–0000000: Sets the device address for the
two-wire serial mode. This setting overrides the value set
on the SA[3:0] pins. The SA3 pin must be HIGH during
the write operation to enable a write to this register.
3.4.21
Reserved
This register is for Vitesse use only.
Table 46.
Register 7A’h: Reserved
Bit Name
Access Description
R/W Reserved. Vitesse use only.
7:0 Reserved
3.4.22
Reserved
This register is for Vitesse use only.
Table 47.
Register 7B’h: Reserved
Bit Name
Access Description
Default
7:5 Reserved
4:3 Reserved
2:1 Reserved
R
Reserved. Vitesse use only.
000
00
00
0
R/W
R
Reserved. Vitesse use only.
Reserved. Vitesse use only.
Reserved. Vitesse use only.
0
Reserved
R/W
Revision 2.0
September 2010
Confidential
Page 42
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
