VSC6134
Datasheet
6.2
Thermal Specifications
Thermal specifications for this device are based on the JEDEC standard EIA/JESD51-2 and have been
modeled using a four-layer test board with two signal layers, a power plane, and a ground plane (2s2p
PCB). For more information, see the JEDEC standard.
Table 471. Thermal Resistances
θ
JA (°C/W) vs. Airflow (ft/min)
Part Order Number
VSC6134ST
θJC
0.5
0.5
0.5
0.5
0
100
10.5
10.5
10.5
10.5
200
14.6
14.6
14.6
14.6
8.5
8.5
8.5
8.5
VSC6134XST
VSC6134ST-01
VSC6134XST-01
To achieve results similar to the modeled thermal resistance measurements, the guidelines for board
design described in the JEDEC standard EIA/JESD51 series must be applied. For information about
specific applications, see the following:
EIA/JESD51-5, Extension of Thermal Test Board Standards for Packages with Direct Thermal
Attachment Mechanisms
EIA/JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
EIA/JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
EIA/JESD51-10, Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements
EIA/JESD51-11, Test Boards for Through-Hole Area Array Leaded Package Thermal Measurements
6.3
Moisture Sensitivity
This device is rated moisture sensitivity level 4 as specified in the joint IPC and JEDEC standard
IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standard.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
