VSC6134
Datasheet
5.1.9
RLL Interface Pins
The following table contains the descriptions for the RLL interface pins.
Table 466. RLL Interface Pins
Pin
Name
I/O Type
Description
AF2
RLLUPP
TO
RLL mode up pulse, PFD mode PFD_P, External mode
CLK.
AF1
AF3
AG1
RLLUPN
RLLDNP
RLLDNN
TO
TO
TO
RLL modeup pulse inverted, External mode SYNC
pulse.
RLL mode down pulse, PFD mode PFD_N, External
mode DATA.
RLL mode down pulse inverted.
5.1.10
JTAG Interface Pins
The following table contains the descriptions for the JTAG interface pins.
Table 467. JTAG Interface Pins
Pin
Name
I/O Type
Description
AH31
TDI
TIU
JTAG data in. This signal is sampled on the rising edge
of TCK. This input has an internal pull-up resistor.
AH32
TMS
TIU
JTAG test mode select. This signal controls the JTAG
test operations (tie high to VDD-IO (2.5 V) for functional
operation). This signal is sampled on the rising edge of
TCK. This input has an internal pull-up resistor.
AH34
AG31
TDO
TO
TIU
JTAG test data out. This signal is updated on the falling
edge of TCK. TDO is tristated except when scanning of
data is enabled.
TRSTN
JTAG test reset. Active low asynchronous JTAG test
reset. This input has an internal pull-up resistor.
TRSTN must be asserted during the power-up
sequence. During normal operation, the JTAG port
must be held in its reset state.
AH33
TCK
TID
JTAG test clock. This signal provides timing for test
operations. This input has an internal pull-down
resistor.
5.1.11
Scan Test Pins
The following table contains the descriptions for the scan test pins.
Table 468. Scan Test Pins
Pin
Name
I/O Type
Description
G3
DI
TID
Functional output driver inhibit (tie low for functional
operation). This input has an internal pull-down
resistor.
418 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
