VSC6134
Datasheet
Table 464. Serial SONET/SDH Overhead FPGA Interface Pins (continued)
Pin
Name
I/O Type
Description
AD2
DRTXSDHOHFS
TO
TX SONET/SDH overhead frame sync output for the
drop path.
5.1.8
VCXO Interface Pins
The following table contains the descriptions for the VCXO interface pins.
Table 465. VCXO Interface Pins
Pin
Name
I/O Type
TO
Description
AG34
AF32
AH1
AH2
AF34
VCO00
VCO01
VCO10
VCO11
PFD0P
Add path transmit clock (VCOSRC0) divided output.
Add path receive clock (RXCLK1) divided output.
Drop path transmit clock (VCOSRC1) divided output.
Drop path receive clock (RXCLK0) divided output.
TO
TO
TO
TO
Programmable phase detector (PFD) output for the
add path.
AF33
AG3
AG2
AE33
AF4
PFD0N
TO
TO
TO
TI
Programmable phase detector (PFD) output (inverted)
for the add path.
PFD1P
Programmable phase detector (PFD) output for the
drop path.
PFD1N
Programmable phase detector (PFD) output (inverted)
for the drop path.
RXCLK0DIV
RXCLK1DIV
Receive clock for the add path used by the add path
programmable divider.
TI
Receive clock for the drop path used by the drop path
programmable divider.
G22
VCOSRC0_P
VCOSRC0_N
VCOSRC1_P
VCOSRC1_N
PFD1D_P
LIT
LIT
LIT
LIT
LO
LO
LO
LO
VCO TX clock input for the add path.
G23
AH25
AH24
AH13
AH12
G10
VCO TX clock input for the drop path.
Programmable phase detector (PFD) output
(differential) for the drop path.
PFD1D_N
PFD0D_P
Programmable phase detector (PFD) output
(differential) for the add path.
G11
PFD0D_N
417 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
