VSC6134
Datasheet
Table 462. Client Tx Interface Pins (continued)
Pin
Name
I/O Type
LO
Description
AP2
AN2
AL2
AK2
AH10
AH9
TXDATA115_P
TXDATA115_N
TXCLK1_P
Data15 output for the client serializer IF (single-edge
clocking). This is the MSB.
LO
LO
Tx clock output for the client serializer IF (single-edge
clocking).
TXCLK1_N
LO
TXCLKSRC1_P
TXCLKSRC1_N
LIT
Tx clock input for the client serializer IF (single-edge
clocking).
LIT
5.1.6
Serial OTU DW Overhead FPGA Interface Pins
The following table contains the descriptions for the serial OTU DW overhead FPGA interface.
Table 463. Serial OTU DW Overhead FPGA Interface Pins
Pin
Name
I/O Type
Description
Y34
ADDOHCLK1
TO
DW overhead clock for the add path overhead
extraction. This clock is used by the external FPGA to
receive OTU DW overhead data (RXOCHD1), frame
sync (RXOCHFS1), and stuff bytes (RXSTFD1).
Y33
RXOCHD1
RXOCHFS1
RXSTFD1
TO
TO
TO
TO
Receive OTU DW overhead data output for the add
path.
W33
AD34
AB32
Receive OTU DW overhead frame sync output for the
add path.
Receive OTU DW overhead stuff data output for the
add path.
ADDOHCLK0
DW overhead clock for the add path overhead
insertion. This clock is used by the external FPGA to
transmit OTU DW overhead data (TXOCHD0), frame
sync (TXOCHFS0), and stuff bytes (TXSTFD0).
AE34
AD32
AA3
TXOCHD0
TI
TI
Transmit OTU DW overhead data input for the add
path.
TXOCHFS0
TXSTFD0
Transmit OTU DW overhead frame sync input for the
add path.
TI
Transmit OTU DW overhead stuff data input for the add
path.
AC1
DROPOHCLK0
TO
DW overhead clock for the drop path overhead
extraction. This clock is used by the external FPGA to
receive OTU DW overhead data (RXOCHD1), frame
sync (RXOCHFS1), and stuff bytes (RXSTFD1).
AB2
AC2
RXOCHD0
TO
TO
Receive OTU DW overhead data output for the drop
path.
RXOCHFS0
Receive OTU DW overhead frame sync output for the
drop path.
415 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
