VSC6134
Datasheet
Table 463. Serial OTU DW Overhead FPGA Interface Pins (continued)
Pin
Name
I/O Type
Description
AD33
RXSTFD0
TO
Receive OTU DW overhead stuff data output for the
drop path.
AE4
DROPOHCLK1
TO
DW overhead clock for the drop path overhead
insertion. This clock is used by the external FPGA to
transmit OTU DW overhead data (TXOCHD1), frame
sync (TXOCHFS1), and stuff bytes (TXSTFD1).
AE2
AE3
AB1
TXOCHD1
TXOCHFS1
TXSTFD1
TI
TI
TI
Transmit OTU DW overhead data input for the drop
path.
Transmit OTU DW overhead frame sync input for the
drop path.
Transmit OTU DW overhead stuff data input for the
drop path.
5.1.7
Serial SONET/SDH Overhead FPGA Interface Pins
The following table contains the descriptions for the serial SONET/SDH overhead FPGA interface.
Table 464. Serial SONET/SDH Overhead FPGA Interface Pins
Pin
Name
I/O Type
Description
AA33
ADSDHOHCLK
TO
SONET/SDH overhead clock for the add path
overhead insertion and extraction. This clock is used
by the external FPGA to capture RX SONET/SDH
overhead data (ADRXSDHOHD) and frame sync
(ADRXSDHOHFS), and to insert TX SONET/SDH
overhead data (ADTXSDHOHD) using frame sync
(ADTXSDHOHFS).
AA34
Y32
ADRXSDHOHD
ADRXSDHOHFS
TO
TO
RX SONET/SDH overhead data output for the add
path.
RX SONET/SDH overhead frame sync output for the
add path.
AB34
AB33
ADTXSDHOHD
ADTXSDHOHFS
TI
TX SONET/SDH overhead data input for the add path.
TO
TX SONET/SDH overhead frame sync output for the
add path.
AD3
DRSDHOHCLK
TO
SONET/SDH overhead clock for the drop path
overhead insertion and extraction. This clock is used
by the external FPGA to capture RX SONET/SDH
overhead data DRRXSDHOHD) and frame sync
(DRRXSDHOHFS), and to insert TX SONET/SDH
overhead data (DRTXSDHOHD) using frame sync
(DRTXSDHOHFS).
AE1
AD1
AC3
DRRXSDHOHD
DRRXSDHOHFS
DRTXSDHOHD
TO
TO
TI
RX SONET/SDH overhead data output for the drop
path.
RX SONET/SDH overhead frame sync output for the
drop path.
TX SONET/SDH overhead data input for the drop path.
416 of 438
VMDS-10185 Revision 4.0
July 2006