VSC6134
Datasheet
Table 420. Global MPU Register 26 - Drop SONET Enables
Reset
Value
Bit
Name
Access
Description
7
AS_TOHI_S1_EN
R/W
Drop path serial interface SONET transport
overhead insertion enable of S1 byte.
0: SONET S1 insertion disabled
0
1: SONET S1 insertion enabled
6
AS_TOHI_E2_EN
R/W
Drop path serial interface SONET transport
overhead insertion enable of E2 byte.
0: SONET E2 insertion disabled
0
1: SONET E2 insertion enabled
5:1
0
Reserved
RO
0x00
1
AS_LOHM_EN
R/W
Drop path SONET line overhead monitor enable.
0: SONET line overhead monitor disabled
1: SONET line overhead monitor enabled
3.13.24 Global MPU Register 27 - Phase/Frequency Discriminator Register
Address:
0x01B
Register Reset Value:
0x0000
Table 421. Global MPU Register 27 - Phase/Frequency Discriminator Register
Reset
Value
Bit
Name
Access
Description
15
ADD_RX_CLOCK_SELECT
R/W
0: Selects RXCLK1 as the clock source.
1: Selects RXCLK0DIV as the clock source.
0
14
ADD_CLOCK_RATIO_LATCH
R/W
A 0 to 1 transition of this bit causes the values
programmed in the Add Path divide ratio registers
(see Table 422, page 384 and Table 423, page 384)
to be transferred to their corresponding counters.
0
13
12
DROP_RX_CLOCK_SELECT
DROP_CLOCK_RATIO_LATCH
R/W
R/W
0: Selects RXCLK0 as the clock source.
1: Selects RXCLK1DIV as the clock source.
0
0
A 0 to 1 transition of this bit causes the values
programmed in the Drop Path divide ratio registers
(see Table 424, page 384 and Table 425, page 385)
to be transferred to their corresponding counters.
11:1
0
Reserved
RO
0x000
0
ADD_CLIENT_CLK_SEL
R/W
Add path client clock select.
0: Use RXCLK1 (normal operation).
1: Use TXCLKSRC0 (for SONET AIS-L generation
when RXCLK1 does not meet minimum
requirements).
383 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
