VSC6134
Datasheet
3.13.20 Global MPU Register 19 - Correction Register
Address:
0x013
Register Reset Value:
0xF001
Table 417. Global MPU Register 19 - Correction Register
Reset
Value
Bit
Name
Access
Description
15
EFEC1_DEC_EN
R/W
Configuration bit used to enable error correction in
EFEC Decoder 1.
0: EFECDecoder 1 is not enabled for correction
(errors are monitored).
1
1
1
1
1: EFECDecoder 1 is enabled for correction.
14
13
12
EFEC1A_DEC_EN
EFEC2_DEC_EN
EFEC2A_DEC_EN
R/W
R/W
R/W
Configuration bit used to enable error correction in
EFEC Decoder 1A.
0: EFECDecoder 1A is not enabled for correction
(errors are monitored).
1: EFECDecoder 1A is enabled for correction.
Configuration bit used to enable correction in EFEC
Decoder 2.
0: EFECDecoder 2 is not enabled for correction
(errors are monitored).
1: EFECDecoder2 is enabled for correction.
Configuration bit used to enable error correction in
EFEC Decoder 2A.
0: EFECDecoder 2A is not enabled for correction
(errors are monitored).
1: EFECDecoder 2A is enabled for correction.
11:4
3:1
0
Reserved
RO
RO
0x00
000
1
Reserved
DROP_RS_DEC_EN
R/W
Configuration bit used to enable drop standard FEC
decoder.
0: Line drop RS decoder is not enabled
1: Line drop RS decoder is enabled
3.13.21 Global MPU Register 20 - SerDes Control Register
Address:
0x014
Register Reset Value:
0x3C00
Table 418. Global MPU Register 20 - SerDes Control Register
Reset
Value
Bit
Name
Access
Description
15
CLIENT_DATA_LB
R/W
Configuration bit used to create a loopback from
RXDATA1[15:0] to TXDATA1[15:0].
0: No loopback.
0
1: Loopback mode.
379 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
