VSC6134
Datasheet
3.10.6
Add/Drop FEC Frame Aligner Register 0
Address:
0xD08: Add Path
0x100: Drop Path
0xF000
Register Reset Value:
Table 382. Add/Drop FEC Frame Aligner Register 0
Reset
Value
Bit
Name
Access
Description
15
FEC_FERM
R/W
Mask bit for FER interrupt status bit.
1: Mask interrupt
1
0: Allow FER status bit to generate interrupt
14
13
12
FEC_OOFM
FEC_LOFM
FEC_LOSM
Reserved
R/W
R/W
R/W
RO
Mask for OOF interrupt status bit.
1: Mask interrupt
0: Allow OOF status bit to generate interrupt
1
Mask for LOF interrupt status bit.
1: Mask interrupt
0: Allow LOF status bit to generate interrupt
1
1
Mask for LOS interrupt status bit.
1: Mask interrupt
0: Allow LOS status bit to generate interrupt
11:0
0x000
3.10.7
Add/Drop FEC Frame Aligner Register 1
Address:
0xD09: Add Path
0x101: Drop Path
0xA600
Register Reset Value:
Table 383. Add/Drop FEC Frame Aligner Register 1
Reset
Value
Bit
Name
Access
Description
15:14
FEC_FRAMECTRL[1:0]
R/W
Framing pattern control.
00: A1A2
10
01: A1A2A2
10: A1A1A2A2
11: Reserved
13
12
FEC_DESCRAM_ENA
FEC_FORCE_OOF
R/W
R/W
0: Descrambler is disabled.
1: Descrambler is enabled.
1
0
A 0 to 1 transition of this bit forces the frame aligner to
reframe and it generates new NFA regardless of position of
framing pattern.
11
10
FEC_LOS_FE
R/W
R/W
A 1 causes the frame aligner to force an OOF when a
falling edge of LOS is detected and new NFA is generated
regardless of position of framing pattern.
0
1
FEC_INTEGRATING_TIMER
A 1 puts the OOF timer in the integrating mode.
355 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
