VSC6134
Datasheet
3.10
Frame Aligner for the SONET, ODU, and OTU Frames
The frame aligner for SONET, ODU, and OTU frames registers and configuration bits are shown in the
following sections. For information about the function and description of the frame aligner for the
SONET, ODU, and OTU frames, see “Frame Aligner for SONET, ODU, and OTU Frames,’ page 140.
The OTU frame aligner registers are shown in tables: 382, 383, 384, 385, and 386. The addresses
starting at 0x100 correspond to the drop OTU frame aligner and the addresses starting at 0xD08
correspond to the add OTU frame aligner.
3.10.1
Add/Drop SONET Frame Aligner Register 0
Address:
0xD00: Add Path
0x500: Drop Path
0xF000
Register Reset Value:
Table 377. Add/Drop SONET Frame Aligner Register 0
Reset
Value
Bit
Name
Access
Description
15
FERM
R/W
Mask bit for FER interrupt status bit.
1: Mask interrupt
1
0: Allow FER status bit to generate interrupt
14
13
12
SEFM
R/W
R/W
R/W
RO
Mask for SEF interrupt status bit.
1: Mask interrupt
0: Allow SEF status bit to generate interrupt
1
LOFM
Mask for LOF interrupt status bit.
1: Mask interrupt
0: Allow LOF status bit to generate interrupt
1
1
LOSM
Mask for LOS interrupt status bit.
1: Mask interrupt
0: Allow LOS status bit to generate interrupt
11:0
Reserved
0x000
3.10.2
Add/Drop SONET Frame Aligner Register 1
Address:
0xD01: Add Path
0x501: Drop Path
0xA600
Register Reset Value:
Table 378. Add/Drop SONET Frame Aligner Register 1
Reset
Value
Bit
Name
Access
Description
15:14
FRAMECTRL[1:0]
R/W
Framing pattern control
00: A1A2
10
01: A1A2A2
10: A1A1A2A2
11: Reserved
352 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
