VSC6134
Datasheet
Table 378. Add/Drop SONET Frame Aligner Register 1 (continued)
Reset
Value
Bit
Name
Access
Description
13
DESCRAM_ENA
R/W
0: Descrambler is disabled
1: Descrambler is enabled.
1
12
11
FORCE_SEF
LOS_FE
R/W
R/W
A 0 to 1 transition of this bit forces the frame aligner to
reframe, and it generates new NFA regardless of position of
framing pattern.
0
A 1 causes the frame aligner to force a SEF when a falling
edge of LOS is detected, and new NFA is generated
regardless of position of framing pattern.
0
10
9
INTEGRATING_TIMER
AUTO_SEF
R/W
R/W
A 1 puts SEF timer in the integrating mode.
1
1
A 0 disables framing bit errors from forcing SEF. A 1
enables framing bit errors to force SEF.
8:0
Reserved
RO
0x000
3.10.3
Add/Drop SONET Frame Aligner Register 2
Address:
0xD02: Add Path
0x502: Drop Path
0x205C
Register Reset Value:
Table 379. Add/Drop SONET Frame Aligner Register 2
Reset
Value
Bit
Name
Access
Description
15:13
INFRAME_CTRL[2:0]
R/W
Determines the number of consecutive frames with valid
framing pattern to clear the SEF condition. Number of
frames is (INFRAME_CTRL + 1).
001
12:2
LOFCLRCNT[10:0]
R/W
Determines the number of frames for which SEF signal
should remain de-asserted to clear the LOF condition.
Number of frames is (LOFCLRCNT +1).
0x17
1
0
MASK_GEN_NFA
Reserved
R/W
RO
A 1 masks the generate NFA request.
0
0
353 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
