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VSC6134XST-01 参数 Datasheet PDF下载

VSC6134XST-01图片预览
型号: VSC6134XST-01
PDF下载: 下载PDF文件 查看货源
内容描述: [Micro Peripheral IC,]
分类和应用:
文件页数/大小: 438 页 / 4019 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
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VSC6134  
Datasheet  
3.8.55  
DW Tandem Connection Monitor BEI Count Register (LSW)  
This is a paged register. Select one of six TCMs as defined in Table 250, bits [2:0].  
Address:  
0xF37: Add Path  
0x737: Drop Path  
0x0000  
Register Reset Value:  
Table 256. DW Tandem Connection Monitor BEI Count Register (LSW)  
Reset  
Value  
Bit  
Name  
Access  
Description  
15:0  
TCM_BEICNT[15:0]  
RO  
TCM BEI counter LSW  
0x00  
3.8.56  
DW Path Monitor TTI FIFO Access Register  
Address:  
0xF38: Add Path  
0x738: Drop Path  
0x0000  
Register Reset Value:  
Table 257. DW Path Monitor TTI FIFO Access Register  
Reset  
Value  
Bit  
Name  
Access  
Description  
15:0  
PM_TTI  
RO  
This register provides access to a 32-word deep, 16-bit  
wide FIFO that holds the monitored path TTI values. The  
FIFO has one configurable pointer for both read and write  
operations shown in Table 258. Each time a read or write  
operation occurs at this address (0xF38 Add / 0x738 Drop)  
the pointer is automatically incremented by 1. Each of the  
32 registers in the FIFO contains two 8-bit values for TTI.  
Received TTI values are entered into the FIFO on a rotating  
basis. The value of bits [7:0] of address 00000 of the FIFO  
represents TTI 0 and the value at bits [15:8] of address  
11111 of the FIFO represents TTI 64. The 64-byte TTI  
signal is aligned with the OTU multiframe (MFAS). Byte 0 of  
the 64-byte TTI signal is present at OTU multiframe  
position 00.  
0x0000  
310 of 438  
VMDS-10185 Revision 4.0  
July 2006  
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