VSC6134
Datasheet
Table 162. Add/Drop Encoder OTU/Client Maintenance Signal Controls (continued)
Reset
Value
Bit
Name
Access
Description
10
[ADD/DROP]_LOF_AIS
R/W
1: ODU-AIS inserted automatically when LOF detected by
[ADD/DROP] Frame Aligner
0
9
[ADD/DROP]_LOFD_AIS
[ADD/DROP]_ODU_OCI_EN
[ADD/DROP]_LOS_OCI
[ADD/DROP]_LOSD_OCI
[ADD/DROP]_ODU_LCK_EN
Reserved
R/W
R/W
R/W
R/W
R/W
RO
1: ODU-AIS inserted automatically when LOF detected by
Drop/Add Frame Aligner
0
0
8
1: ODU-OCI forced insertion when this bit is set high
regardless of other conditions
7
1: ODU-OCI inserted automatically when LOS detected on
[ADD/DROP] RSOH block.
0
6
5
1: ODU-OCI inserted automatically when LOS detected by
Drop/Add FEC block.
0
1: ODU-LCK forced insertion when this bit is set high
regardless of other conditions
0
4:0
0x00
3.6.10
Add/Drop Test Error Generator Counter MSB Register
Address:
0x809: Add Path
0x289: Drop Path
0x0000
Register Reset Value:
Table 163. Add/Drop Test Error Generator Counter MSB Register
Reset
Value
Bit
Name
Access
Description
15:0
ERRFREQ1
R/W
16-bit MSB value of the error counter. This value is
prepended to ERRFREQ0. The total value is decremented
every clock cycle TXCLKSRC0 until reaching 0. The error
is injected if ERROR_ENA = 1.
0x0000
3.6.11
Add/Drop Test Error Generator Counter LSB Register
Address:
0x80A: Add Path
0x28A: Drop Path
0x0000
Register Reset Value:
Table 164. Add/Drop Test Error Generator Counter LSB Register
Reset
Value
Bit
Name
Access
Description
15:0
ERRFREQ0
R/W
16-bit LSB value of the error counter. This value is
appended to ERRFREQ1. The total value is decremented
every clock cycle TXCLKSRC0 until reaching 0. The error
is injected if ERROR_ENA = 1
0x0000
261 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
