VSC6134
Datasheet
3.4.7
TX LOH Generator E2 Byte Configuration Register
Address:
0xFF2: Add Path
0x7F2: Drop Path
0x0000
Register Reset Value:
Table 142. TX LOH Generator E2 Byte Configuration Register
Reset
Value
Bit
Name
Access
R/W
Description
[15:8]
[7:0]
TX_E2BYTE
Reserved
E2 byte for insertion
0x00
0x00
R/W
3.4.8
TX LOH Generator Line DCC Bytes Configuration Registers
Address:
0xF80 to 0xFEB: Add Path
0x780 to 0x7EB: Drop Path
0x0000
Register Reset Value:
Table 143. TX LOH Generator Line DCC Bytes Configuration Registers
Reset
Value
Bit
Name
Access
Description
15:0
TX_DCCXY[15:8]
R/W
Line data communication channel bytes:
0x0000
TX_DCC(X+1)Y[7:0]
There are 108 addresses that each contain two line DCC
bytes. The first address contains: D1224, D41, the second
address contains D51, D61, ..., and the 108th address
contains D1024, D1124.
3.4.9
TX LOH Generator E2 and Line DCC Interrupt Mask Register
Address:
0xFF3: Add Path
0x7F3: Drop Path
0x0000
Register Reset Value:
Table 144. TX LOH Generator E2 and Line DCC Interrupt Mask Register
Reset
Value
Bit
Name
Access
Description
15
TX_DCCRDY_M
R/W
0: Allows TX_DCCRDY_S interrupt status register to
generate an interrupt
1
1: Disables TX_DCCRDY_S interrupt status register from
generating interrupts
14
TX_E2RDY_M
Reserved
R/W
RO
0: Allows TX_E2RDY_S interrupt status register to
generate an interrupt
1: Disables TX_E2RDY_S interrupt status register from
generating interrupts
1
13:0
0x0000
249 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
