VSC6134
Datasheet
Table 151. SOH Source Configuration Registers (continued)
Reset
Value
Bit
Name
Access
Description
10
F1_SOURCE
R/W
A 1 forces F1 to be regenerated. A 0 passes F1 through
transparently.
0
0
0
0
0
9
8
7
6
DCC_SOURCE
A1A2_SOURCE
FER_INSERT
AISAUTOENA
R/W
R/W
R/W
R/W
A 1 forces DCC bytes to be regenerated. A 0 passes the
DCC bytes through transparently.
A 1 forces A1/A2 bytes to be regenerated. A 0 passes the
A1/A2 bytes through transparently.
A 1 forces errors to be inserted in the framing pattern for
test purposes.
A 1 forces AIS-L to be transmitted upon detection of LOF or
LOS defects.
5
4
AISMANUENA
R/W
R/W
A 1 forces manual AIS-L insertion.
0
0
BIPERR_INSERT
A 1 forces errors to be inserted in the BIP-8 (B1) byte for
test purposes.
3
2
1
0
TX_J0CNTRL
TX_SCRENA
R/W
R/W
R/W
R/W
A 0 selects the insertion of 64 byte sequence. A 1 selects
the insertion of the 16-byte SAPI sequence.
1
1
0
0
A 0 disables the SDH scrambler. A 1 enables the SDH
scrambler.
RESERV_SOURCE
RS_AIS_EN
A 1 forces the reserve bytes to be regenerated. A 0 passes
reserve bytes through transparently.
A 1 forces RS-AIS (J0 = 0xFF) to be generated during the
transmission of AIS-L. A 0 disables the transmission of RS-
AIS.
3.5.7
SOH Generator Interrupt Mask Registers
Address:
0xEA7: Add Path
0x6A7: Drop Path
0x0000
Register Reset Value:
Table 152. SOH Generator Interrupt Mask Registers
Reset
Value
Bit
Name
Access
Description
15
TX_DCCRDYM
R/W
Mask bit for TX_DCCRDYS interrupt status bit.
1: Mask interrupt.
1
0: Allow TX_DCCRDYS status bit to generate the interrupt.
14:0
Reserved
RO
0x0000
253 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
