VSC6134
Datasheet
Table 136. TX LOH Generator General Configuration Register (continued)
Reset
Value
Bit
Name
Access
Description
8
RDI_AIS_EN
R/W
RDI-L AIS-L enable.
0
0: A detected opposite path AIS-L condition does not cause
the same path RDI-L transmission.
1: A detected opposite path AIS-L condition causes the
same path RDI-L transmission if TX_K2MD_AUTO is set.
7
TX_LINE_BYPASS
R/W
Line bypass control.
0
0: Line overhead bytes are sourced by the line overhead
generator (depending on their respective configurations).
1: Line overhead bytes are passed through transparently.
6
5
4
TX_B2ERR_INSRT
TX_M0M1ERR_INSRT
TX_M0M1_INSRT
R/W
R/W
R/W
Forced B2 error insertion control.
0: B2 errors are not forced.
1: B2 errors are forced.
0
0
0
Forced M0 and M1 errors insertion control.
0: M0 and M1 bytes errors are not forced.
1: M0 and M1 bytes errors are forced.
M0 and M1 bytes insertion mode.
0: M0 and M1 bytes are not inserted.
1: M0 and M1 bytes are inserted.
3
2
Reserved
RO
0
0
TX_RESERV
R/W
Indicates the fixed stuff pattern to transmit in the line
overhead reserve bytes.
0: Transmit 0x55 in the reserve bytes.
1: Transmit 0xAA in the reserve bytes.
1
TX_M0M1_SELECT
Reserved
R/W
RO
Selects between M1 mode only or the M0/M1 mode.
0: M0/M1 mode.
1: M1 mode only.
0
0
0
3.4.2
LOH Generator K1 and K2 Bytes Configuration Register
Address:
0xFED: Add Path
0x7ED: Drop Path
0x0000
Register Reset Value:
Table 137. LOH Generator F1 and K2 Bytes Configuration Register
Reset
Value
Bit
Name
Access
Description
15:0
TX_K1K2BYTE
R/W
K1 (TX_K1K2BYTE[15:8]) and K2 (TX_K1K2BYTE[7:0])
bytes for insertion
0x0000
246 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
