VSC6134
Datasheet
3.4.6
LOH Generator Source Configuration Register
Address:
0xFF1: Add Path
0x7F1: Drop Path
0x0000
Register Reset Value:
Table 141. LOH Generator Source Configuration Register
Reset
Value
Bit
Name
Access
Description
15
TX_DCC_SOURCE
R/W
Indicates the source of the line DCC byte.
0: Pass the line DCC bytes through transparently.
1: Source line DCC bytes.
0
0
0
0
0
0
0
14
13
12
11
10
9
TX_S1_SOURCE
TX_E2_SOURCE
AISP_AISL_EN
AISP_LOF_EN
AISP_LOS_EN
AISP_LOC_EN
R/W
R/W
R/W
R/W
R/W
R/W
Indicates the source of the S1 byte.
0: Pass the S1 byte through transparently.
1: Source S1 byte.
Indicates the source of the E2 bytes.
0: Pass the E2 byte through transparently.
1: Source E2 byte.
Indicates whether AIS-L causes AIS-P generation.
0: AIS-L does not cause AIS-P.
1: AIS-L causes AIS-P.
Indicates whether LOF causes AIS-P generation.
0: LOF does not cause AIS-P.
1: LOF causes AIS-P.
Indicates whether LOS causes AIS-P generation.
0: LOS does not cause AIS-P.
1: LOS causes AIS-P.
Indicates whether loss of clock (LOC) causes AIS-P
generation.
0: LOC does not cause AIS-P.
1: LOC causes AIS-P.
8
7
6
5
TX_B2_SOURCE
TX_RESERV_SOURCE
TX_Z1_SOURCE
TX_Z2_SOURCE
R/W
R/W
R/W
R/W
Indicates the source of the B2 byte.
0: Pass the B2 byte through transparently.
1: Source B2 byte.
0
0
0
0
Indicates the source of the line reserve bytes.
0: Pass the reserve bytes through transparently.
1: Source reserve bytes.
Indicates the source of the Z1 bytes.
0: Pass the Z1 bytes through transparently.
1: Source Z1 bytes as configured by TX_RESERV.
Indicates source of Z2 bytes.
0: Pass the Z2 bytes through transparently.
1: Source Z2 bytes as configured by TX_RESERV.
Note: In M1 only mode, Z2 is present where M0 is in M0/M1
mode.
4:0
Reserved
R/W
0x0
248 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
