VSC6134
Datasheet
3.4.3
TX LOH Generator S1 Byte Configuration Register
Address:
0xFEE: Add Path
0x7EE: Drop Path
0x0000
Register Reset Value:
Table 138. TX LOH Generator S1 Byte Configuration Register
Reset
Value
Bit
15:8
7:0
Name
Access
R/W
Description
TX_S1BYTE
Reserved
S1 byte for insertion
0x00
0x00
R/W
3.4.4
LOH Generator B2 Error Configuration Register
Address:
0xFEF: Add Path
0x7EF: Drop Path
0x0000
Register Reset Value:
Table 139. LOH Generator B2 Error Configuration Register
Reset
Value
Bit
Name
Access
Description
15:8
TX_B2ERR_MSK
R/W
Bit mask for B2 error insertion. This mask byte is XOR’d
with each of the 192 B2 bytes per STS-192 frame.
0x00
7:0
Reserved
RO
0x00
3.4.5
LOH Generator M0 and M1 Error Configuration Register
Address:
0xFF0: Add Path
0x7F0: Drop Path
0x0000
Register Reset Value:
Table 140. LOH Generator M0 and M1 Error Configuration Register
Reset
Value
Bit
Name
Access
Description
15:0
TX_M0M1ERR_REG
R/W
M0 and M1 error count. Allows you to introduce any
number of errors for testing the M0 and M1 bytes
(1536 errors maximum for M0/M1 mode; 255 maximum for
M1 mode).
0x0000
247 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
