VSC6134
Datasheet
2.15.5
FEC Bridge with On-Chip DWOH Processing Modes
There are two DWOH Processing FEC Bridge modes:
●
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StFEC(S) <-DWOH (with payload processing)-> LFEC(S), 1/1
StFEC(NS) <-DWOH (with payload processing)-> LFEC(NS), 1/1
The following figure shows the FEC bridge or regenerator with on-chip DWOH processing and with
synchronously mapped SONET or 10 GbE payload monitoring (no regeneration). In the add direction,
the StFEC signal is framed, decoded, and optionally corrected; DWOH performance monitoring is
performed; and the DWOH is terminated or passed through. The synchronously mapped payload
(SONET or 10 GbE) is monitored. New DWOH is then inserted as required, and the LFEC parity bytes
are recalculated and added. In the drop direction, the LFEC signal is framed, decoded, and optionally
corrected; DWOH performance monitoring is performed; and the DWOH is terminated or passed
through. The synchronously mapped payload (SONET or 10 GbE) is monitored, new DWOH is then
inserted as required, and the StFEC parity bytes are recalculated and added.
System and line side rates are the same. When transporting 10 GbE payload, the device is overclocked.
The StFEC(S) to LFEC(S) mode supports the optional extraction to the OTU stuff bytes received in the
add and drop directions, and the insertion of the OTU stuff bytes transmitted in the add and drop
directions.
Figure 39. StFEC to LFEC Bridge with Payload Monitoring Mode
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
