VSC6134
Datasheet
2.14.1
PRBS Generator (PRBSGEN)
The PRBS generator block generates a continuos pseudo-random binary sequence of selectable length.
The sequences are generated by maximal length LFSRs operating in 64-bit parallel mode.
The PRBS generator block I/O is shown in the following table.
Table 62. PRBS Generator Block I/O Description
Name
Direction
IN
Function
clk
System clock
resetn
IN
Active low system reset
Active low MPU reset
MPU clock
mpu_resetn
mpu_clk
IN
IN
mpu_wrena
mpu_rdena
mpu_wdata[15:0]
prbsgen_select
prbsgen_rdata
prbsgen_dtk
prbs_out[63:0]
IN
MPU write enable
IN
MPU read enable
IN
MPU write data
IN
MPU block select
OUT
OUT
OUT
MPU read data
MPU data acknowledge
Pseudo random binary sequence output to serializer
The PRBS generator block is enabled by the PRBSGEN_ENA configuration bit and generates a
continuous sequence (of 64-bit parallel data) of length selected by the PRBSGEN_SEL[1:0] bits (see
“Add PRBS Generator Configuration Register,” page 359). The output sequence is optionally inverted if
the PRBSGEN_INV bit is asserted. The LFSR state bits are reset to all ones for all polynomials.
149 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
