VSC6134
Datasheet
2.12
Phase-Frequency Discriminator
The digital phase-frequency discriminator is designed to work in a phase-locked loop system as shown
in the following figure.
Figure 33. Phase-Locked Loop Application Example
Drop Path
On-Chip
Add Path
Reference Input
f
RXCLK1DIV
RXCLK0
RXCLK0DIV
RXCLK1
1/N
Prescaler
f / N
Loop
Filter
VCO
PFD
f / N
f × M / N
1/M
VCOSRC0
VCOSRC1
Prescaler
Oscillator Output
When the reference and oscillator inputs are at or near lock, the PFD outputs produce the desired output
waveform duty-cycle. All PFD outputs have both standard LVTTL and standard LVDS outputs.
o
When the reference and oscillator waveforms are exactly 180 out of phase, the PFD output duty-cycle
is exactly 50% and the PFD is operating in locked mode. When the oscillator waveform leads or lags the
reference waveform, the duty-cycle of the PFD output is adjusted accordingly.
Holdover reference clocks RXCLK0DIV and RXCLK1DIV are necessary to keep PLL going when
RXCLK0 or RXCLK1 input clocks are lost and are not provided by the external transceivers in LOS
condition.
2.12.1
Phase/Frequency Discriminator Register Information
For information about the phase/frequency discriminator registers, see “Phase/Frequency Discriminator
Registers,” page 358.
145 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
