VSC6134
Datasheet
2.13
SerDes Interface and Clock Generation
The on-chip deserializer block demultiplexes and synchronizes a 16-bit data stream received at
622 Mbps (SONET/SDH Rx), 669 Mbps (OTU Rx), or 666 Mbps (StFEC or EFEC Rx) into a 64-bit
data stream at one-fourth the input rate.
The on-chip serializer block multiplexes and synchronizes 64-bit data delivered at either 155 Mbps
(SONET/SDH Tx), 167 Mbps (OTU Tx), or 195 Mbps (SuperFEC Tx) into a 16-bit data stream
delivered at 622 Mbps, 669 Mbps, or 666 Mbps, respectively.
Note, all of the above rates are in reference to the throughput of one of 16 interface bits.
2.13.1
Deserializer Overview
The on-chip deserializer block demultiplexes and synchronizes a 16-bit data-stream received at
622 Mbps (client-side SONET/SDH Rx), 669 Mbps (client-side or line-side OTU Rx), 645 Mbps
(client-side 10GbE Rx), 780 Mbps (line-side SFEC Rx) and 806 Mbps (line-side SFEC Rx) into a 64-bit
datastream at 1/4 of the input rate.
The deserializer I/O descriptions are shown in the following table.
Table 60. Deserializer Block I/O Description
Name
Direction
Function
hw_reset_n
sw_reset_n
rxclkin16
IN
IN
Hardware reset—Primary input.
Software reset generated by microprocessor interface.
High-speed clock—Primary input.
IN
rxclkout16
rxdin[15:0]
syrxsclk64
sysrxclk64_reset_n
rxclk64
IN
High-speed clock—to serializer for loopback operation.
High-speed data in synced to rxclkin16—Primary inputs.
Low-speed system clock from clock tree.
Reset synchronized to sysrxclk64.
IN
IN
IN
OUT
Low-speed system clock from clock divider (1/4 frequency of
high-speed clock) to system clock-tree.
rxdout[63:0]
OUT
Low-speed 64-bit parallel data out synced to system clock—
sysrxclk64.
2.13.2
Serializer Overview
The on-chip serializer block multiplexes and synchronizes 64-bit data delivered at either 155 Mbps
(client side SONET/SDH Tx), 167 Mbps (client/line side OTU Tx), 195 Mbps (line side SFEC Tx), and
202 Mbps (line side SFEC Tx) into a 16-bit data stream delivered at 781 Mbps (line side SFEC Tx),
669 Mbps (client/line side OTU Tx), and 805 Mbps (client side 10 GbE with SFEC Tx), respectively.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
