VSC6134
Datasheet
Parity bytes are represented by:
R(z) = R × z + R × z + ... + R × z + R
0
15
14
1
(EQ 5)
(EQ 6)
15
14
1
where R (j = 0 to 15) is the parity byte represented by an element out of GF(256) and
j
R = r × α 7 + r × α 6 + ... + r × α 1 + r
j
7j
6j
1j
0j
Bit r is the MSB and r is the LSB of the parity byte. R corresponds to the byte 240 in the RS
7j
0j
15
codeword and R to byte 255.
0
R(z) is calculated by R(z) = I(z) mod G(z), where mod is the modulo calculation over the code
generator polynomial G(z) with elements out of the GF(256). Each element in GF(256) is defined by the
8
4
3
2
binary primitive polynomial x + x + x + x + 1.
The hamming distance of the RS(255,239) code is dmin=17. The code can correct up to 8 symbol errors
in the FEC codeword when it is used for error correction. The FEC can detect up to 16 symbol errors in
the FEC codeword when it is used for error detection capability only.
1.2.2
EFEC
This section describes the structure of the concatenated BCH-BCH code for forward error correction
(FEC) as related to the structure of the VSC6134 EFEC device. The EFEC algorithm uses the same
number of bits in its frame as the standard OTU frame (4 x 4080 x 8). It also uses the same framing
pattern. Complete digital wrapper overhead content is preserved.
The parity overhead of the concatenated code is:
255
-------- = 1.066949
239
1.2.2.1
Framing Structure and Interleaving
The concatenated code consists of 16 outer BCH(3904,3832) codewords and 32 inner BCH(2040,1952)
codewords.
The framing and interleaving details are:
●
Two rows of the G.709 frame (3824 bytes) are encoded within 16 outer BCH(3904,3832) codes; the
outer BCH code has 8 bits (out of 3832 bits) that are used for an internal CRC computation.
●
●
The outer code is 32-way interleaved onto 32 inner BCH(2040,1952) codes.
The inner code is 32-way muxed onto a serial stream.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
