VSC6134
Datasheet
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On-chip generation and termination of the OTU digital wrapper overhead bytes MFAS (multiframe
indication), BIP-8 (bit interleaved parity), TTI (trail trace identifier), and BI (backward indication).
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On-chip generation and detection of OTU-AIS, ODU-AIS, OCI and LCK.
On-chip termination of BIP-8 including detection and accumulation of single bit and block errors.
Synchronous payload mapping and demapping.
Bit error and Framed PRBS insertion and detection for test and verification.
Optional correction of the FEC signalregeneration of the tandem connection monitoring fields
(BIP-8, TTI, BDI, BEI, STAT). Six TCM fields can be processed simultaneously.
1.1.5
Ethernet Monitor Features
The Ethernet monitor features are:
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Digitally wraps the 10.3125 GbE LAN-PHY client by device overclocking
Reports the 64b/66b code violations
PCS loss of synchronization and BER monitoring
PCS test pattern error monitoring
Managed objects, MIB and RMON statistics counters, sized for a minimum of 57-minute
monitoring intervals
1.1.6
General Features
The general features are:
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16-bit Intel and Motorola-compatible microprocessor interfaces
Loss of input clock (LOCK) detection on all clock inputs
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PRBS generation and detection provisionable for 2 – 1, 2 – 1, 2 – 1, 2 – 1
Provisionable FEC bypass (SONET/SDH transparent pass through)
Provisionable FEC and SDH regenerator loopback
Provisionable for regenerator or terminal functions
Simplified clocking scheme with an integrated divider and phase frequency detector
622/706 MHz LVDS interfaces for low crosstalk on the PC board
FIFO overflow and underflow detection with an optional auto-reframe
IEEE 1149.1-compliant boundary scan through a JTAG interface
Power supply of 1.2 V for the core and 2.5 V and 3.3 V for the peripheral I/O
Power down for EFEC decoders when in the Non-EFEC mode
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
